JVD Press Release

Press Contact: Bob Frostholm
Phone: +1-408-263-7704
Email: bob [dot] frostholm [at] jvdinc [dot] com

JVD and Thermal Engineering Associates Develop Thermal Test Chip

TTC-1002 by TEA Simplifies Semiconductor Package Thermal Characterization

San Jose, CA June 10, 2008 – JVD Inc., the leader in Analog Mixed-Signal ASIC and Test Services, and Thermal engineering Associates. Inc. (TEA) the leader in thermal measurement, modeling, and solutions for semiconductor packaging, announced today the availability of the TTC-1002 Thermal Test Chip from TEA.

The Thermal Test Chip was conceived by TEA and designed by JVD for use in semiconductor package thermal characterization and electronic system thermal management design activities. The device meets JEDEC JESD51-4 Thermal Test Chip Guidelines. “JVD’s stellar record of quality and reliability coupled with strong technical support made them our first choice for the program,” said Bernie Siegel, TEA Founder and CEO.

2.5mm x 2.5mm TTC unit cellexample 3×3 array of cells

The 2.5mm x 2.5mm TTC unit cell is shown top left and an example 3×3 array of cells is shown top right. The TTC wafers are available in either wire-bond (with inter-cell connection, so only periphery wire-bonding is required) or bump-chip (with each cell electrically isolated) form. Each wafer contains a 40×40 array of unit cells can easily be sawn into various sub-array sizes to meet specific die dimensions in unit cell increments. The wafers can be thinned and backside treated on a custom basis.

The TTC 1102 features:

  • Multiple diode sensors for measurement of die temperature contours
  • Multiple heating resistors for uniform and non-uniform heating setup
  • Designed for square or rectangular array applications
  • Kelvin connection for heating resistors to improve thermal measurement accuracy
  • Multiple sizes to accommodate a wide range of package characterization requirements
  • Supplied in wafer form, allowing for user-specific backside treatment
  • Wafer designed with metal interconnection between die to eliminate inter-cell wire bond requirements

About Thermal Engineering Associates
TEA, started in 1997, and its president, Bernie Siegal, a 43+ year industry veteran, have been providing thermal test and measurement hardware, software, and consulting services for several decades. Siegal has been chairman of the JEDEC JC15 committee and is the principle author of many MILSTD 750 thermal test methods. All major semiconductor companies, packaging companies, and many system level OEMs have utilized TEA products and/or services during its long history. Siegal is a founding member of IEEE SEMI-THERM, has delivered numerous papers and articles on thermal testing, and is frequently sought out as a lecturer and expert in the field. For more information on products and services, go to www.thermengr.com.

About JVD, Inc.
JVD is a leader in the design and production of Custom Analog Semiconductors, known as Analog ASICs.  These cost effective, high performance devices meet and exceed customer’s challenging design requirements by lowering total system cost, shrink size by reducing the number of components required and thwart product pirates by embedding IP that can not be copied. Founded in 1982 by Jerry VanDierendonck, a member of the TI team that developed the world’s first microprocessor, TMS 1000, JVD is a privately held company with headquarters in San Jose, Calif. For more information, please visit www.jvdinc.com.

© 2008 JVD Inc